1. Field of Invention
The present invention relates to a memory device structure and a method for manufacturing the same. More particularly, the present invention relates to a memory structure and a method for manufacturing the same, which can improve reliability by using the raised bit line.
2. Description of Related Art
Memory is widely applied In the integrated circuit industry and plays an especially essential role in the electronic industry. For the storage of digital data, the capacitance of the memory is called a xe2x80x9cbitxe2x80x9d and the unit for data storage in a memory is called a xe2x80x9cmemory cellxe2x80x9d. The memory cells are arranged in an array, consisting of columns and rows. Between a set of columns and rows, the specific position of each memory cell is an address. A common wiring line, which is called a word line, couples memory cells in the same column or the same row. Another wiring line vertical to the common wiring line is called a bit line.
FIG. 1 illustrates a cross-sectional view of a prior art memory structure. Referring to FIG. 1, a gate oxide layer 102 is formed on a substrate 100. Next, a buried bit line 104 is formed in the substrate 100. A field oxide insulation layer 106 is formed on the buried bit line 104 to Isolate the buried bit line and a subsequent word line. Afterwards, a word line 108 is formed on the field insulation layer 106 and the gate oxide layer 102, in a direction perpendicular to the buried bit line 104.
As the demand for high-density memory increases, the width of the buried bit-lines in memory becomes smaller to satisfy the demand. The smaller the width of the bit line, the higher the resistance, thus reducing the current of the memory cell and inducing higher bit-line loading. However, if the junction depth of the bit line is Increased to improve the aforementioned problems, new issues, including short channel effects and junction leakage, can arise. On the other hand, if heavy dosage implantation is used to reduce the resistance, solid solubility limitation may hamper application of heavy dosage implantation for forming shallow junction for the bit lines. Moreover, in the prior memory device structure, at least one bit line contact is arranged for every 32 or 64 bit lines to control the memory device, which restrains further Improvements toward higher integration. Therefore, it is significant to decrease the number of the bit line contacts for increasing Integration of the device.
Accordingly, the present invention provides a memory structure and a method for manufacturing the memory structure, which can reduce the resistance of bit lines.
Accordingly, the present invention provides a memory structure and a method for manufacturing the memory structure, which can allow shallow junctions for buried bit lines, thus preventing short channel effects and junction leakage.
Accordingly, the memory structure and the method for manufacturing the memory device structure of the present invention can decrease the number of the bit line contact in the device, thus increasing device Integration.
As embodied and broadly described herein, the invention provides a memory structure, comprising: a substrate; a gate oxide layer disposed on a portion of the substrate; a gate disposed on the gate oxide layer; a buried bit line disposed in the substrate along both sides of the gate; a raised line disposed on the buried bit line; a spacer disposed on both sidewalls of the gate structure, thus isolating the gate and the raised line; a word line disposed on the gate in a direction perpendicular to the buried bit line; and an insulation layer disposed on a top of the raised line to electrically isolate the word line and the raised line. The bit line of the present invention consists of the raised line and the underlying buried bit line.
As embodied and broadly described herein, the invention provides a method for manufacturing a memory structure, comprising; forming a thin oxide layer, a first conductive layer and a material layer on the substrate sequentially; patterning the first conductive layer and the material layer to form the bar-shaped conductive structure and the cap layer; forming a buried bit line in the substrate along both sides of the bar-shaped conductive structure by using the cap layer as a mask; removing the thin oxide layer that is not covered by the bar-shaped conductive structure, so that the remained thin oxide layer underneath the bar-shaped conductive structure is the gate oxide layer; forming a spacer on sidewalls of the bar-shaped conductive structure with a first etching selectivity between the cap layer and the spacer; forming a raised line on the buried bit line, while the spacer isolates the bar-shaped conductive structure and the raised line; forming an insulation layer on the raised line to electrically isolate a subsequent word line and the raised line, with a second etching selectivity between the cap layer and the insulation layer; removing the cap layer; and forming a second conductive layer over the substrate to cover the bar-shaped conductive structure; and forming the word line and a plurality of gates over the substrate by patterning the second conductive layer and the bar-shaped conductive structure in a direction perpendicular to the buried bit line. The word line is electrically connected to the gates on the same row.
It Is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.